For the fabrication of integrated circuits, layers provided with different electrical properties are usually applied on semiconductor wafers and in each case patterned lithographically. A lithographic patterning step may consist in applying a photosensitive resist, exposing the latter with a desired structure for the relevant plane and developing it, and then transferring the resultant resist mask into the underlying layer in an etching step.
For the lithographic projection step of a circuit pattern, a wafer scanner or wafer stepper is usually used as exposure apparatus. In the exposure apparatus, the photosensitive resist is exposed with electromagnetic radiation having a predetermined wavelength, for example lying in the UV range.
Each individual layer of the circuit pattern is usually imaged onto the semiconductor wafer using a special mask (also called reticle) and a projection optical arrangement. The reticle comprises a substrate layer provided with absorbent elements, such as e.g. a chromium layer, which simulate the circuit pattern. The projection optical arrangement of the exposure apparatus often contains a plurality of lenses and diaphragms and often reduces the circuit pattern during transfer onto the resist layer.
Dense line-gap patterns such as are formed for instance in the field of fabricating dynamic random access memories have feature sizes of 70, 90 or 110 nm, by way of example. During the process of lithographic exposure of such a pattern, wavelengths of 248 nm or 193 nm are used nowadays in the exposure apparatuses.
The structure resolution that can be achieved is influenced by a plurality of factors. In this case, it has been found, inter alia, that densely packed structures are imaged onto the resist layer with a different linewidth than isolated or semi-isolated structures. Furthermore, a shortening of lines to be imaged at their ends and also an altered linewidth are observed. In order to minimize the inaccuracies resulting from these effects during lithographic projection, critical structure elements are often provided with so-called OPC structures. OPC structures (OPC=optical proximity correction) alter the form or dimensions of specific structure elements at specific locations of the circuit pattern, or are additional structures that are not imaged in the photoresist.
In order to determine the OPC structures, the circuit pattern is usually calculated using a simulation model of the photolithographic projection which results during imaging onto the resist layer of the semiconductor wafer. A simulation model that calculates the physical-chemical processes during lithography by means of a two-dimensional model is often used for this purpose. These calculations have to be executed for virtually the entire area of the reticle in order to be able to calculate the OPC structures for the entire chip to be fabricated.
It has been shown, however, that the two-dimensional models often used are beset by errors since important physical effects cannot be taken into account on the basis of the two-dimensional consideration.
In recent years lithographic simulation has implemented refined, but more complex computational methods that enable physical-chemical processes in lithographic technology to be modeled and calculated as closely to reality as possible. Small regions of the reticle can be simulated accurately by means of these complex simulations. These simulation models cannot be used for a large-area application since the required computation times would be orders of magnitude too long. Examples of accurate simulation models are the so-called transfer matrix model and other three-dimensional simulation models.